The invention pertains to semiconductor wafer assemblies comprising silicon nitride layers, and to methods of forming silicon nitride layers during semiconductor wafer processing.
Modern semiconductor wafer fabrication frequently incorporates silicon nitride layers into process steps. For example, silicon nitride layers can be utilized to electrically insulate conductive components. As another example, silicon nitride layers can be utilized to protect regions of a semiconductive wafer during local oxidation of silicon (LOCOS).
An example prior art LOCOS fabrication process is described with reference to FIGS. 1-3. Referring to FIG. 1, a semiconductor wafer fragment 10 comprises a substrate 12 having a pair of opposing surfaces 14 and 16. Substrate 12 can comprise, for example, monocrystalline silicon lightly doped with a p-type dopant. To aid in interpretation of the claims that follow, the term xe2x80x9csemiconductive substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Silicon dioxide layers 18 and 20 are formed over surfaces 14 and 16, respectively, and silicon nitride layers 22 and 24 are formed over silicon dioxide layers 18 and 20, respectively. Silicon dioxide layers 18 and 20 function as pad oxide layers to protect substrate 12 from stress induced by silicon nitride layers 22 and 24. Silicon dioxide layers 18 and 20 can be formed by, for example, exposing a silicon-comprising substrate 12 to an oxygen ambient to grow layers 18 and 20 from the silicon of the substrate. Silicon nitride layers 22 and 24 can be formed by, for example, chemical vapor deposition of silicon nitride over silicon dioxide layers 18 and 20.
Silicon nitride layers 22 and 24 typically comprise Si3N4. Si3N4 often requires discrete antireflective coating layers intermediate it and an overlying photoresist layer. Accordingly, Si3N4 does not have very good inherent antireflective properties. Antireflective coatings are utilized during photolithographic processing of photoresist layers to absorb light passing through the photoresist layers. Antireflective coatings can thereby prevent light from being reflected from beneath the photoresist layer to constructively and/or destructively interfere with other light propagating through the photoresist layer.
Although Si3N4 generally requires discrete antireflective coating layers intermediate it and an overlying photoresist layer, silicon enriched silicon nitride layers (i.e., silicon nitride layers having a greater concentration of silicon than Si3N4, such as, for example, Si4N4) frequently do not. However, silicon enriched silicon nitride is difficult to pattern due to a resistance of the material to etching. Silicon enriched silicon nitride layers are formed to have a substantially homogenous composition throughout their thicknesses, although occasionally a small portion of a layer (1% or less of a thickness of the layer) is less enriched with silicon than the remainder of the layer due to inherent deposition problems.
Silicon oxide layer 18 and silicon nitride layer 22 are utilized in formation of LOCOS over substrate 12. The remaining silicon oxide and silicon nitride layers (layers 20 and 24) are not utilized for formation of LOCOS, but rather are provided to equalize a stress across substrate 12. If layers 18 and 22 are provided without also providing layers 20 and 24, it is found that substrate 12 can deform. More specifically, silicon nitride layer 22 exerts a tensile force against surface 14 of substrate 12. Such tensile force can bow outer edges of substrate 12 downwardly unless it is balanced by a tensile force exerted on opposing surface 16 of substrate 12. Thus, silicon nitride layer 24 is provided proximate opposing surface 16 to exert a tensile force which balances the tensile force of silicon nitride layer 22.
Referring to FIG. 2, a patterned photoresist layer 26 is provided over layers 22 and 18. Patterned photoresist layer 26 defines LOCOS regions 28 of upper surface 14 of substrate 12.
Referring to FIG. 3, portions of layers 18 and 22 are removed to expose LOCOS regions 28 of upper surface 14. In subsequent processing that is not shown, patterned photoresist layer 26 is removed and field oxide is formed at LOCOS regions 28. The forming of field oxide can comprise, for example, exposing wafer fragment 10 to an oxidizing atmosphere to grow the field oxide.
A difficulty of the above-described process can occur when portions of layers 18 and 22 are removed. After such removal, there is less of upper silicon nitride layer 22 relative to lower silicon nitride layer 24. Thus, the tensile force provided by bottom silicon nitride layer 24 may no longer be balanced by the tensile force of upper silicon nitride layer 22. Accordingly, outer edges of substrate 12 can undesirably be bowed upwardly by the tensile force of bottom silicon nitride layer 24. Such bowing of the substrate can adversely affect subsequent processing steps. For instance, the bowing can cause mask misalignment in subsequent photolithography steps. It would be desirable to develop methods of LOCOS processing whereby bowing of substrate 12 is substantially eliminated. More generally, it would be desirable to develop methods of semiconductor wafer processing whereby silicon nitride induced pressures on a semiconductor wafer are alleviated.
In one aspect, the invention encompasses a method of forming a silicon nitride layer over a surface of a semiconductive wafer. The silicon nitride layer comprises at least two portions. One of the at least two portions generates a compressive force against the other of the at least two portions, and the other of the at least two portions generates a tensile force against the one of the at least two portions.
In another aspect, the invention encompasses a method of reducing stress on semiconductive wafer. The semiconductive wafer has a pair of opposing surfaces and has a greater amount of silicon nitride over one of the opposing surfaces than over an other of the opposing surfaces. The silicon nitride over the one of the opposing surfaces comprises a first portion, a second portion and a third portion. The first, second and third portions are elevationally displaced relative to one another, and the second portion is between the first and third portions. The second portion has a greater stoichiometric amount of silicon than the first and third portions. The semiconductive wafer is subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness.
In yet another aspect, the invention encompasses a semiconductive wafer assembly. The assembly comprises a semiconductive wafer substrate having a pair of opposing surfaces and a first silicon nitride layer over one of the opposing surfaces. The first silicon nitride layer comprises a first portion, a second portion and a third portion. The first, second and third portions are elevationally displaced relative to one another, and the second portion is between the first and third portions. The second portion has a greater stoichiometric amount of silicon than the first and third portions.